/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-18 10:55:38
 *
 */


#ifndef REG_FW0_AP_H
#define REG_FW0_AP_H

#define CTL_BASE_REG_FW0_AP 0x32809000


#define REG_REG_FW0_AP_REG_RD_CTRL_0          ( CTL_BASE_REG_FW0_AP + 0x0000 )
#define REG_REG_FW0_AP_REG_WR_CTRL_0          ( CTL_BASE_REG_FW0_AP + 0x0004 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY0   ( CTL_BASE_REG_FW0_AP + 0x0008 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY1   ( CTL_BASE_REG_FW0_AP + 0x000C )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY2   ( CTL_BASE_REG_FW0_AP + 0x0010 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY3   ( CTL_BASE_REG_FW0_AP + 0x0014 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY4   ( CTL_BASE_REG_FW0_AP + 0x0018 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY5   ( CTL_BASE_REG_FW0_AP + 0x001C )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY6   ( CTL_BASE_REG_FW0_AP + 0x0020 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY7   ( CTL_BASE_REG_FW0_AP + 0x0024 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY8   ( CTL_BASE_REG_FW0_AP + 0x0028 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY9   ( CTL_BASE_REG_FW0_AP + 0x002C )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY10  ( CTL_BASE_REG_FW0_AP + 0x0030 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY11  ( CTL_BASE_REG_FW0_AP + 0x0034 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY12  ( CTL_BASE_REG_FW0_AP + 0x0038 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY13  ( CTL_BASE_REG_FW0_AP + 0x003C )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY14  ( CTL_BASE_REG_FW0_AP + 0x0040 )
#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY15  ( CTL_BASE_REG_FW0_AP + 0x0044 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY0        ( CTL_BASE_REG_FW0_AP + 0x0048 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY1        ( CTL_BASE_REG_FW0_AP + 0x004C )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY2        ( CTL_BASE_REG_FW0_AP + 0x0050 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY3        ( CTL_BASE_REG_FW0_AP + 0x0054 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY4        ( CTL_BASE_REG_FW0_AP + 0x0058 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY5        ( CTL_BASE_REG_FW0_AP + 0x005C )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY6        ( CTL_BASE_REG_FW0_AP + 0x0060 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY7        ( CTL_BASE_REG_FW0_AP + 0x0064 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY8        ( CTL_BASE_REG_FW0_AP + 0x0068 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY9        ( CTL_BASE_REG_FW0_AP + 0x006C )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY10       ( CTL_BASE_REG_FW0_AP + 0x0070 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY11       ( CTL_BASE_REG_FW0_AP + 0x0074 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY12       ( CTL_BASE_REG_FW0_AP + 0x0078 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY13       ( CTL_BASE_REG_FW0_AP + 0x007C )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY14       ( CTL_BASE_REG_FW0_AP + 0x0080 )
#define REG_REG_FW0_AP_BIT_CTRL_ARRAY15       ( CTL_BASE_REG_FW0_AP + 0x0084 )

/* REG_REG_FW0_AP_REG_RD_CTRL_0 */

#define BIT_REG_FW0_AP_APB_EB1_RD_SEC            BIT(4)
#define BIT_REG_FW0_AP_EB_SEC_RD_SEC             BIT(3)
#define BIT_REG_FW0_AP_APB_MISC_CTRL_RD_SEC      BIT(2)
#define BIT_REG_FW0_AP_APB_RST_RD_SEC            BIT(1)
#define BIT_REG_FW0_AP_APB_EB_RD_SEC             BIT(0)

/* REG_REG_FW0_AP_REG_WR_CTRL_0 */

#define BIT_REG_FW0_AP_APB_EB1_WR_SEC            BIT(4)
#define BIT_REG_FW0_AP_EB_SEC_WR_SEC             BIT(3)
#define BIT_REG_FW0_AP_APB_MISC_CTRL_WR_SEC      BIT(2)
#define BIT_REG_FW0_AP_APB_RST_WR_SEC            BIT(1)
#define BIT_REG_FW0_AP_APB_EB_WR_SEC             BIT(0)

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY0 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY0(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY1 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY1(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY2 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY2(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY3 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY3(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY4 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY4(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY5 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY5(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY6 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY6(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY7 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY7(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY8 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY8(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY9 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY9(x)   (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY10 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY10(x)  (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY11 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY11(x)  (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY12 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY12(x)  (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY13 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY13(x)  (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY14 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY14(x)  (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY15 */

#define BIT_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY15(x)  (((x) & 0xFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY0 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY0(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY1 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY1(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY2 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY2(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY3 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY3(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY4 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY4(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY5 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY5(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY6 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY6(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY7 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY7(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY8 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY8(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY9 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY9(x)        (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY10 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY10(x)       (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY11 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY11(x)       (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY12 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY12(x)       (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY13 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY13(x)       (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY14 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY14(x)       (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AP_BIT_CTRL_ARRAY15 */

#define BIT_REG_FW0_AP_BIT_CTRL_ARRAY15(x)       (((x) & 0xFFFFFFFF))


#endif /* REG_FW0_AP_H */


